A 60-year-old fork in the road reappears: the ternary chip that almost beat binary
The entire silicon empire—your phone, the cloud, the GPU scalping your paycheck—rests on a coin toss: 0 or 1. Claudio Lorenzo La Rosa just reminded everyone that the coin once had three sides. His 5500FP, booted in a garage this spring, is the first general-purpose ternary processor since the Soviets shut down the Setun in 1965. Twenty-four trits, 20 MHz, etched into an off-the-shelf FPGA. Numbers that sound quaint until you realize they reopen a question the industry buried alive for economic convenience, not technical merit.
The elegance knuth couldn’t stop quoting
Donald Knuth called balanced ternary “the most beautiful number system” for a reason. Negative numbers don’t need a sign bit; you flip a trit from −1 to +1 and keep moving. Multiplication becomes symmetric, carries vanish, and the silicon never wastes a transistor on two’s-complement gymnastics. In 1958 the Moscow State team squeezed 18 kg of hardware into a cabinet that outperformed contemporary binary beasts on raw MIPS per watt. The catch: vacuum tubes hate three stable states. When TTL logic arrived, the binary freight train was already moving too fast to jump off.
Why the fork lost
Texas Instruments didn’t conspire against elegance; it just had a warehouse full of NAND gates that only knew high and low. Retooling lithography masks for −1, 0, +1 thresholds would have vaporized quarterly earnings. Path dependence dressed up as destiny. The binary victory was a supply-chain accident, not a theorem.
Fpga sleight of hand
La Rosa’s hack is brutally pragmatic: every trit is two binary LUTs pretending. The mapping wastes 33 % of the transistor budget, but it also ships today, no 3-level masks required. Native atomic synchronization, 120-instruction RISC ISA, and a GCC fork that emits tritcode prove the toolchain can live in 2026. Twenty megahertz is laughable—until you notice that the demo board idles at 0.8 W while mining SHA-3 hashes at the same joule-per-hash ratio as a 3 GHz Cortex-A78. Efficiency sometimes hides in low clocks, not high hype.
Silicon or it didn’t happen
The FPGA is a stunt double. A real ternary fab process—think 3-level flash cells already storing eight discrete voltages—could push the same design to 4 GHz and shave 40 % area off the register file. The problem is that no foundry keeps a −1 doped threshold library in its PDK. La Rosa is shopping a 180 nm shuttle run at IMEC this winter; if the shuttle fills, the cost per mm² drops below 0.05 USD. At that price, a ternary DSP for hearing aids or phased-array radar becomes someone’s side-project, not a moonshot.
The market that binary forgot
Machine-learning people keep complaining about bfloat noise accumulation; trits natively encode sign-magnitude without rounding. Signal-processing folks crave symmetric multiply-accumulate; ternary delivers it in a single cycle. Cryptographers want modular arithmetic on 257-bit primes; balanced bases collapse carry propagation. None of these niches justify a 50-billion-dollar fab, but they don’t need to. A 22 nm ternary accelerator tacked onto an SRAM bus could sip 30 mW while off-loading matrix squaring for a battery sensor that spends 99 % of its life asleep. The volume is small, the margin obscene.
History’s second draft
The Setun wasn’t defeated; it was deferred. La Rosa’s board is a reminder that technological lock-in is only as permanent as the last accountant who refused to recalculate the spreadsheet. If the foundry run tapes out and the first wafers boot Lua 5.4 on a 1.2 V trit rail, the narrative flips: binary becomes the legacy mode, the compatibility layer, the guest in an emulator. Sixty years late, the coin finally lands on its edge—and stays there.